MIPS 處理器 數據通路設計 verilog代寫

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EECE 3324
Computer Architecture and Organization
Final Project
MIPS Architecture Implementation
Due on Apr. 14th (M) 11:59pm
Basic project: single-cycle MIPS architecture implementation (worth 25% of the total course points)
1. Overview
For the EECE3324 project, you will implement the standard single-cycle MIPS architecture in Verilog. You are given a memory Verilog file which contains both text (program instructions) and data, you should write a processor Verilog file which contains all the modules for the processor datapath and controller. The processor module interacts with the memory module. You should write your own testbench file to simulate the processor and memory. Finally, you should calculate the CPI of the provided program from the Verilog simulator.
I recommend using Modelsim as the HDL simulator. Instruction file on Modelsim installation and usage have been posted on BB. You can also use others, like ISE simulator, vcs, etc., if you are familiar with them. However, you have to let the TA and me

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