Verilog/VHDL 作業輔導

<标题>Verilog/VHDL程序輔導 Verilog/VHDL編程作業

CSCE614 solution supersalar

CSCE614 Computer Architecture (Spring 2015)

<标题>Homework #4 (Pseudo-Associative Cache)

(Due: Beginning of class on 4/17/2015)

Objective

This project is to help you understand how pseudo-associative (column-associative) cache works. You

will initially analyze the sensitivity of L1 caches to changes in parameters. Then you are to implement L1

data cache as pseudo-associative in SimpleScalar and compare its performance to the normal direct-
mapped L1 data cache.

<标题>System Requirement

<标题>Linux operating system is needed in order to use the pre-compiled little-endian Alpha ISA SPEC2000

binaries. Do not use Cygwin. If you don’t have any linux machine, please use linux.cs.tamu.edu with your

CS account. If you don’t have CS account, contact HelpDesk located in the first floor.

Setting up the environment and installing SimpleScalar

<标题>1. Download and Install SimpleScalar 3.0.

(1) Download simplesim-3v0e.tgz from http://www.simplescalar.com/.

(2) Untar the downloaded file.

<标题>$ tar xzvf simplesim-3v0e.tgz

<标题>(3) Read the

MIPS 處理器 數據通路設計 verilog代寫

1
EECE 3324
Computer Architecture and Organization
Final Project
MIPS Architecture Implementation
Due on Apr. 14th (M) 11:59pm
Basic project: single-cycle MIPS architecture implementation (worth 25% of the total course points)
1. Overview
For the EECE3324 project, you will implement the standard single-cycle MIPS architecture in Verilog. You are given a memory Verilog file which contains both text (program instructions) and data, you should write a processor Verilog file which contains all the modules for the processor datapath and controller. The processor module interacts with the memory module. You should write your own testbench file to simulate the processor and memory. Finally, you should calculate the CPI of the provided program from the Verilog simulator.
<标题> I recommend using Modelsim as the HDL simulator. Instruction file on Modelsim installation and usage have been posted on BB. You can also use others, like ISE simulator, vcs, etc., if you are familiar with them. However, you have to let the TA and me

histogram equalization verilog代寫

ECE 464/520: Project Technical Requirements
You are to produce a Histogram Equalization Unit for image processing. A general description of what a histogram equalization unit does can be found on Wilkipedia amongst other sources,
http://en.wikipedia.org/wiki/Histogram_equalization
You will be processing a series of small (640 x 480 pixel ) images. The images will contain 32-bit unsigned pixels representing gray scale images. A basic description of the algorithm is found below (this is extracted from a requirements document in one of our research projects.
<标题> Change (Feb 6, 2014). The data supplied to you actually has a dynamic range of only 8 bits per pixel. SO that you can all take advantage of this, you only need to produce a histogram where the value of each pixel is sorted into L=28 buckets, not 216 buckets.

 

You have to design a unit that maximizes the number of images that can be processed per unit area. You thus need to report how long (in seconds) it takes to process an image, and what is the cel

FIFO設計 verilog代寫

<标题>同步FIFO的設計思路:

<标题>1.同步FIFO的基本原理:

FIFO(First In First Out)——是一種可以實現數據先入先出的存儲器件。FIFO就像一個單向管道,數據只能按固定的方向從管道一頭進來,再按相同的順序從管道另一頭出去,最先進來的數據必定是最先出去。FIFO被普遍用作數據緩沖器。

<标题>FIFO的基本單元是寄存器,作為存儲器件,FIFO的存儲能力是由其內部定義的存儲寄存器的數量決定的。本題中所設計的是同步FIFO(即輸出輸入端時鐘頻率一致),異步復位,其存儲能力為(4×4,設計的這么小主要是由于板子的寄存器數量非常有限當然也可以使用4×8或者4×16),輸出兩個狀態信號:full與empty,以供后繼電路使用。

<标题>2.本組同步FIFO的設計分析與框架:

同步FIFO整體架構:

解釋與說明:上圖中最大的矩形框所包圍的內部部分為所設計的同步FIFO,由FIFO主控體和RAM構成。FIFO主控體接收來自外部的讀寫控制信號(read_n,write_n)、復位信號(reset_n)和時鐘信號(clock),并在時鐘上升沿到來時根據從RAM返回的counter信號進行讀寫控制判斷以及讀寫指針的計算,并將所得結果以mwrite_n,mread_n,wr_pointer ,rd_pointer信號的形式傳遞給RAM進行相應的讀寫操作。其中counter信號代表RAM體內已存儲未讀數據的數據個數。整個同步FIFO包括八條外部數據信號線(包括總線)和五條內部數據信號線。

 

 

<标题>同步FIFO的具體設計:

程序開始先進行復位判斷,假如復位鍵按下,則進行復位。接著判斷讀信號是否有效,假如無效,則判斷寫是否有效,假如有效,并且存儲體不滿的話則進行寫操作,先產生正確的寫指針,然后將輸入的數據寫入對應的RAM空間內。讀雷同。當讀寫都有效時,counter不做更改,而直接產生讀寫指針,然后進行讀寫操作,當然在讀寫之前要先判斷是否空滿。

arbiter設計部分代碼注釋 verilog代寫

<标题>module top_to_bottom(

input? wire??????? clk,

input? wire??????? rst_n,

<标题>input? wire [15:0] req, //request信號入口? 0~15號分別對應

<标题>output reg? [15:0] grt? //grant 信號出口

);

 

reg [4:0] i;

reg [15:0] grt_tmp;? //定義一個中間變量 方便進行非阻塞賦值 注意這里并沒有產生

//register

 

always @ (*) begin

grt_tmp = 16’b0;? //進行初始賦值 注意不要在posedge clk下賦值 要不然會產生寄存器

<标题>for (i=0;i<5’d16;i=i+1) begin

if (req[i] == 1’b1)

begin

grt_tmp[i] = 1’b1;? //如果對應的node號申請就按照top bottom的優先級放權

<标题>i????? = 5’d15;?? //一旦放權后就退出循環,方法是把i打到最大

end

end

end

 

always @ (posedge clk) begin //進行寄存器賦值操作

if (!rst_n)

<标题>grt <= 16’b0;

else

grt <= grt_tmp;? //

end

endmodule

 

 

module round_robin(

input wire??????? clk,

<标题>input wire??????? rst_n,

<标题>input wire [15:0] req,

<标题>output reg [15:0] grt

);

<标题>reg [3:0] cnt;//一個計數器,相當于一個指針,每當上一次node申請成功后,就指向與此//node相鄰的下一個node,這個信息需要跨時鐘沿,so we need some registers!

reg [3:0] i;

<标题>reg [15:0] grt_tmp;//注意i和grt_tmp在綜合時其實都不是寄存器,雖然他們是reg類型J

 

<标题>always @ (*) begin

i = cnt;

<标题>grt_tmp = 16’b0;

while (rst_

cache設計 verilog代寫

In this assignment, you will design a generic memory block and use it to perform various tasks.

?

Part 1: Memory/cache design.

A physical cache block is made up of memory cells which are associated in rows and columns. Each row corresponds to a cache-line, which may contain any size of data. These lines are then stacked in column form. In general, each cache line consists of 3 major parts, the ID tag, the data, and the state (or status) of each line. The state bits will be ignored for this assignment (just use ID tag and data).

When a request comes in for a line, the cache lines are searched concurrently to determine if a line matches the requested ID tag. If the tag matches, then the bits in the data portion of the cache line are sent out of the system. (Note: this assignment is a scaled down version of a traditional fully-associative cache, not including any sense amplifiers and other support circuitry).

Your job is to design such a cache, with a compile-time vari

IrDA設計 部分說明 verilog代寫

基于IrDA協議的串行通信說明文檔

  1. 串行通信和UART協議

<标题>UAR T (U n i ve rs a l A s ynch r onou s Rece i ve r Tr an s m it 2t e r)協議是一種串行數據傳輸協議 。UAR T允許在串行鏈路上進行全雙工通信 ,在數據通信及控制系統中得到了廣泛運用 。

基本 的 UAR T 通信 只需 要兩 條信號 線 ( R x D ,Tx D )就可以完成數據的全雙工通信任務 。 Tx D 是UAR T發送端 , 為輸出 ; Rx D 是 UAR T 接收端 , 為輸入。UAR T的基本特點是 : 在信號線上共有兩種狀態 ,分別用邏輯 1 ( 高電平 ) 和邏輯 0 ( 低電平 ) 來區分 。 例如 , 在發送器空閑時 , 數據線保持在邏輯高電平狀態 ,發送器是通過發送起始位來開始一個數據幀的傳送 ,起始位使數據線處于邏輯 0 狀態 , 提示接收器數據傳輸即將開始 。 接著發送數據位 ,數據位一般為 8 位一個字節的數據 ( 也有 5 位 、 6 位或 7 位的情況 ) ,低位 (L S B ) 在前 ,高位 (M S B ) 在后 。 然后發送校驗位 ,校驗位一般用來判斷傳輸的數據位有無錯誤 ,一般是奇偶校驗 。停止位在最后 ,用以標識數據傳送的結束 , 它對應于邏輯1 狀態 。

圖1 UART協議格式

(重點)實現UART的verilog代碼時主要分為三個部分,波特率產生模塊、發送模塊、接受模塊。在原代碼file中其本意也主要是這三個模塊,只是本來可以通過實例化兩個波特率產生模塊的任務變成了兩個模塊即txbaud和rxbaud模塊,為了滿足條件:

圖2 要求

  1. Baud Rate

<标题>我們需要調節Baud Rate為57600,那么就需要在txbaud和rxbaud中進行修改:

首先我們要了解波特率發生器的原理,波特率發生器實際上就是分頻器 ,可以根據給定的系統時鐘頻率 ( 晶振時鐘 ) 和要求的波特率算出波特率分頻因子 ,把算出的波

subtractor verilog代寫

  1. Write a structural Verilog code to generate a 2-bit subtractor. The circuit has two 2-bit inputs A and B and outputs S-sum (2-bits) and B-borrow. Write a test bench simulating all possible input combinations and verify your design checking proper output values and delays. To get the gate-level design of the circuit, create (and show in the write-up) the truth table, and then simplify them. (Use Karnaugh maps). Note that you should assume 2s complements for negative numbers.

 

  1. Using the truth table, create a set of user-defined primitives to accomplish the same 2-bit subtractor.

 

  1. Design an 8-to-1 MUX in Verilog. Each input to the MUX is 16-bit in width. You have to write two different modules implementing a MUX:

<标题>1) Using a CASE statement and

2) Using IF-ELSE statements.

Verify each module by writing a test bench and simulating selection of each input line.

 

  1. Write and simulate/test a behavi

ALU設計 verilog代寫

參照“4ALU設計方案”“ALU Projec 圖表更改.pdf”的功能和時序要求,完成以下工作:

  • 完成該ALUHDL設計,給出其HDL代碼。變量命名請參照表1和表2
  • 給出其功能仿真策略;給出測試該ALUHDL代碼;給出功能仿真結果。
  • 完成該ALU 邏輯綜合,請以腳本.tcl形式給出你所加的設計約束條件和相應的綜合結果。
  • 完成該ALU的版圖綜合(可選);完成該ALULVSDRC(可選);完成該ALU的后仿(可選)。

快速進位加法器 verilog代寫

In this project you are asked to design and implement a 32-bit CLA adder circuit by making use of a fast parallel prefix circuit. The CLA circuit should have 32 inputs and 33 outputs, where the 33rd output is the carry- out. The carry-in is set to zero.

The design may be implemented and synthesized in the design tool of your choice. You may use HDL tools or schematic entry for design entry. For simulation and synthesis you are allowed to use Synopsys, Mentor Graphics, or Xilinx FPGA toolkits.

<标题>ou should simulate your design for functional correctness by providing proper inputs. After verifying the implementation synthesize it by selecting an appropriate target FPGA (or ASIC) model. Extract circuit size and critical path delay information from the post synthesis report.

Also design and implement a 32-bit carry-propagate adder. Compare it to your CLA design in terms of circuit size and delay.

You should turn in a printout of the schematic of your circuit, simulation results showing functional correctness, an