快速進位加法器 verilog代寫

<标题>In this project you are asked to design and implement a 32-bit CLA adder circuit by making use of a fast parallel prefix circuit. The CLA circuit should have 32 inputs and 33 outputs, where the 33rd output is the carry- out. The carry-in is set to zero.

The design may be implemented and synthesized in the design tool of your choice. You may use HDL tools or schematic entry for design entry. For simulation and synthesis you are allowed to use Synopsys, Mentor Graphics, or Xilinx FPGA toolkits.

ou should simulate your design for functional correctness by providing proper inputs. After verifying the implementation synthesize it by selecting an appropriate target FPGA (or ASIC) model. Extract circuit size and critical path delay information from the post synthesis report.

<标题>Also design and implement a 32-bit carry-propagate adder. Compare it to your CLA design in terms of circuit size and delay.

You should turn in a printout of the schematic of your circuit, simulation results showing functional correctness, an

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